|PCI Express and PCI:
- Supports 1-lane 2.5 Gb/s PCI Express.
- Utilizes 100-MHz Differential PCI Express Common Reference Clock
- Fully Compliant with PCI Express Base Specification, Revision 1.0a
- Packetized serial traffic with PCI Express split completion protocol
- Automatic retry of bad packets
- 8b/10b signal encoding
- In-band interrupts and messages
- Support of message signaled interrupts
- Fully Compliant with PCI Local Bus Specification, Revision 3.0
- PCI Bus Power Management Interface r1.1 Compliant
|IEEE 1394 Std Support:
- Fully compliant with provisions of IEEE Std 1394-1995 for high-performance serial bus and the IEEE Std 1394a-2000.
- Fully Compliant with 1394 Open Host Controller Interface Specification, Revision 1.1.
- Full IEEE Std 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-by Concatenation, and Port Disable/Suspend/Resume.
- EEPROM Configuration Support to Load the Global Unique ID for the 1394 Fabric
|1394 Bus Transfer Rate:
||IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s, and 400M Bits/s.
|Number of Ports:
FWx2-PCIE10-2: Two FireWire P1394a Cable Ports
- OHCI 1 (FW-6pin X 1)
- OHCI 2 (FW-6pin X 1)
- D0, D1, D2, and D3 power states and PME events per the PCI Bus Power Management Interface Specification
|Bus Power Connector:
with IDE big 4-pin DC +12V power connector